1. Field of the Invention
This technology relates to a decoder for a NAND memory array.
2. Description of Related Art
A traditional NAND flash design has no negative voltage. All the biases are equal to or larger than 0 volt even when doing erase verify, if the erased cell Vt threshold voltage distribution is below 0 volts. Such designs implement a so-called reverse read operation.
Because of the absence of need for negative voltages for an x-decoder in NAND flash memory, NAND flash memory often uses the traditional x-decoder selector.
In US Patent Application Publication 2008/0062760, a negative level shifter provides negative voltages to select and deselect blocks in the NAND memory array, but has no assisting circuitry for positive level shifting. As a result, the PMOS transistors have more demanding operational requirements.
In US Patent Application Publication 2009/0310405, a positive level shifter is followed by a negative level shifter. However, this design still has demanding operational requirements for the PMOS transistors.
It would be desirable for a high voltage switch to have a wide positive and negative voltage range, without demanding operational requirements for the PMOS transistors.